`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/25 22:41:06
// Design Name: 
// Module Name: ex
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ex(
    input rst,
    input [31:0] alu_a,
    input [31:0] alu_b,
    output [31:0] alu_c,
    input [31:0] branch_a,
    input [31:0] branch_b,
    output [1:0] branch_res,
    input [2:0] alu_op,
    input [1:0] branch
    );
    
alu ALU(.rst(rst),
        .alu_a(alu_a),
        .alu_b(alu_b),
        .alu_c(alu_c),
        .branch(branch),
        .alu_op(alu_op)
       ); 

branchcomp BRANCHCOMP(.rst(rst),
                      .branch_a(branch_a),
                      .branch_b(branch_b),
                      .branch_res(branch_res),
                      .branch(branch)
                      ); 
    
endmodule
